1. Field of the Invention
The present invention relates generally to semiconductor device packages including leads that are electrically exposed through the packages and to methods for fabricating such semiconductor device packages. More particularly, the present invention relates to semiconductor device packages in which the leads are substantially encapsulated and to methods for fabricating these semiconductor device packages. The present invention also pertains to the use of stereolithography in the packaging of electronic components.
2. Background of Related Art
The large-scale production of particular types of semiconductor devices poses problems peculiar to the type of die, electronic circuits, external connectors and packaging. So-called chip scale packages are defined as packaged dice having dimensions substantially the same as the die itself, particularly in length and width. The height of the finished package may be greater than the bare die because of the connecting elements (bond pads, lead frame, wire bonds, and external connectors such as solder balls) which are included in the package.
In order to manufacture semiconductor dice in quantity, a wafer comprising a large number of unsingulated dice is typically processed en masse, then scribed or sawn into individual dice. Finishing operations, including packaging, are typically conducted on the singulated dice. As the sizes of connectors on state-of-the-art semiconductor dice are ever decreasing and the connector densities on semiconductor dice are ever increasing, conventional packaging processes are becoming somewhat undesirable.
The sizes of semiconductor device packages are also continually decreasing. State-of-the-art semiconductor device packages are not much larger than the semiconductor dice thereof. These small semiconductor device packages are typically referred to as xe2x80x9cchip-scale packages,xe2x80x9d or xe2x80x9cCSPs.xe2x80x9d Exemplary CSPs and packaging methods are disclosed in the following U.S. Pat. Nos. 4,862,245; 5,304,842; 5,363,279; 5,677,576; 5,684,330; 5,863,812; and 5,894,107.
The conventional transfer molding processes that are often used to package semiconductor dice are, however, somewhat undesirable when chip-scale packages are desired since it is difficult to form very small packages by transfer molding techniques. For example, transfer molding may cause wire sweep of the fine bond wires that are typically used to connect the bond pads of a semiconductor die to the contacts of a carrier substrate or to leads. When small, thin packages are required, transfer molding techniques may also inadequately cover semiconductor dice due to the formation of voids in the package polymer.
In forming a chip-scale package, a supportive, protective polymer layer may be disposed on the active surface of a semiconductor die before or after solder balls or bumps are secured to the bond pads of the semiconductor die.
When conductive structures, such as small solder balls or bumps, have already been attached to the bond pads of semiconductor dice, it is very difficult to apply a substantially void-free, conformal layer over the active surfaces thereof due to the close packing and small interstitial spacing of the conductive structures.
If the polymer layer is disposed on the active surface prior to attaching the solder balls or bumps, openings must be formed through the polymer layer to accommodate the subsequent attachment of solder balls or bumps to the bond pads. Thus, an etching or other more complex step may be required. The current chemical or mechanical methods that are used to expose bond pads through a polymer layer are undesirably time-consuming. Due to small sizes and high density of the bond pads on state-of-the-art semiconductor devices, the precision of such techniques may also be less than desired.
In some packaging techniques, only the active surfaces of semiconductor dice, or portions of the active surfaces thereof, are covered with protective material. The exposed edges of such packaged semiconductor dice remain vulnerable to damage.
None of the art of which the inventor is currently aware teaches a chip-scale package that includes a semiconductor die, leads connected to the bond pads of the semiconductor die, and a stereolithographically formed package that substantially covers the leads, but through which the leads are at least electrically exposed. Moreover, the art does not teach a method for packaging assemblies including one or more semiconductor devices and leads on a multi-device or wafer scale.
In the past decade, a manufacturing technique termed xe2x80x9cstereolithography,xe2x80x9d also known as xe2x80x9clayered manufacturing,xe2x80x9d has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually being effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or xe2x80x9cslicedxe2x80x9d into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer which can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, preexisting object or component to create a larger product.
However, to the inventor""s knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products, including flip-chip semiconductor devices, in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required. Furthermore, stereolithography methods have not been used to package, at the wafer level, large numbers of flip-chip type semiconductor devices of the same or differing configurations to provide packaged devices which become fully sealed upon bonding to a substrate such as a printed circuit board (PCB). In such a method, the precise location and orientation of a number of preexisting components for stereolithographic application of material thereto without the use of mechanical alignment techniques are required to assure precise, repeatable placement of components.
The present invention includes a semiconductor device package with at least one semiconductor die, leads that are electrically connected to bond pads of the semiconductor die, and a package that substantially covers the leads.
The semiconductor die and lead frame may be of any type known in the art. For example, the semiconductor device package may include a leads-over-chip (LOC) type semiconductor die and a compatible lead frame. The bond pads of the semiconductor die can be connected to the leads by conventional means, such as by way of bond wires, thermocompression bonds, or tape automated bonds.
The leads of the semiconductor device package are at least electrically exposed through the package. In one embodiment, a small portion of each lead is physically exposed through the package. The exposed portions of the leads may be recessed below an outer surface of the package, substantially flush therewith, or protrude from the package. Conductive structures, such as balls, bumps, or pillars of metal (e.g., solders) conductive plastics, or conductor filled plastics, may be subsequently secured to the exposed portions of the leads.
In another embodiment, conductive structures that communicate with the leads are exposed through the package, the leads being substantially contained within the package. Exemplary conductive structures that are useful in the semiconductor device package of the present invention include balls, bumps, or pillars of metal (e.g., solders) conductive plastics, or conductor-filled plastics. Preferably, such conductive structures protrude from the package so as to facilitate connection of the semiconductor device package to external components.
The package covers at least the bond pads of the semiconductor die, the most proximate portions of the corresponding leads, and the connectors therebetween. The package may also cover substantially the entire active surface of the semiconductor die, as well as the peripheral edges or back side thereof. The package of the present invention is preferably a chip-scale package, the dimensions of which are preferably only slightly larger than the dimensions of the assembled semiconductor die and leads. The package, which may be fabricated by stereolithographic techniques, may include a plurality of superimposed, contiguous, mutually adhered layers of dielectric material.
According to another aspect, the present invention includes a method for fabricating the package. In a preferred embodiment of the method, a computer-controlled, 3-D CAD initiated process known as xe2x80x9cstereolithographyxe2x80x9d or xe2x80x9clayered manufacturingxe2x80x9d is used to fabricate the package. When stereolithographic processes are employed, each package is formed as either a single layer or a series of superimposed, contiguous, mutually adhered layers of material.
The stereolithographic method of fabricating the packages of the present invention preferably includes the use of a machine vision system to locate the semiconductor devices or other substrates on which the packages are to be fabricated, as well as the features or other components on or associated with the semiconductor devices or other substrates (e.g., solder bumps, contact pads, conductor traces, etc.). The use of a machine vision system directs the alignment of a stereolithography system with each semiconductor device or other substrate for material disposition purposes. Accordingly, the semiconductor devices or other substrates need not be precisely mechanically aligned with any component of the stereolithography system to practice the stereolithographic embodiment of the method of the present invention.
In a preferred embodiment, the packages to be fabricated upon or positioned upon and secured to a semiconductor device component in accordance with the invention are fabricated using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser under control of a computer and responsive to input from a machine vision system, such as a pattern recognition system, to fix or cure selected regions of a layer of a liquid photopolymer material disposed on the semiconductor device or other substrate.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.